Chetan Jonnalagadda

Signal Integrity and Power Integrity Engineer

• Defined DDR5-6400 channel-analysis requirements for 24 read/write and PVT cases using HSPICE, Cadence Sigrity, buffer corners, and JESD79-5 timing criteria, identified the weakest evaluation-board byte lanes and converted the findings into routing and termination constraints.
• Modeled package-to-PCB signal paths, BGA breakouts, and via transitions in HFSS 3D Layout, isolated dominant loss and reflection sources and provided geometry changes for post-layout review.
• Optimized ODT, driver strength, and DQ-to-DQS skew across supported buffer corners, selecting settings and length constraints that improved margin on the weakest DDR5 byte lanes.
• Analyzed NEXT/FEXT coupling, layer assignments, trace spacing, and reference-plane continuity, and recommended routing and ground-stitching changes to protect memory-channel eye opening.
• Converted rail-noise allocations into regulator-to-package VDD/VDDQ PDN targets by modeling regulator, package, PCB, and decoupling behavior, and provided power-delivery guidance for board design reviews.
• Investigated PDN antiresonance, ESR/ESL, and mounting-inductance effects in SIwave and OptimizePI, and selected capacitor values and placement changes that improved the modeled impedance profile.
• Performed DC IR-drop and current-density analysis across copper paths and power/ground vias, specified wider delivery paths and revised via connections that were adopted in the next board spin.
• Ranked decoupling alternatives using HSPICE load-step analysis for droop, overshoot, and settling behavior, selected the configuration with the strongest transient margin against the rail budget.
• Established VNA, TDR, and oscilloscope test setups for channel loss, impedance, eye margin, and rail-noise measurements, created repeatable comparisons between board revisions.
• Updated fixture, via, and channel models using measured data and achieved insertion-loss correlation within 0.5 dB at 6 GHz, improved confidence in simulation-based design decisions.
• Automated Touchstone validation, corner sweeps, eye analysis, and impedance reporting with Python, reduced weekly report preparation time from 6 hours to 2 hours.
• Coordinated three routing and decoupling changes with PCB layout and package-modeling teams, delivered channel and rail-margin evidence for design reviews and validation reruns.

Signal Integrity Engineer

• Evaluated 32 GT/s PCIe 5.0 channels in Keysight ADS by cascading package, PCB, connector, and via networks with IBIS-AMI models, ranked limiting channels for layout and equalization optimization.
• Decomposed channel loss across packages, traces, connectors, and vias, identified the interconnect segments consuming the most eye and BER margin and prioritized them for corrective action.
• Selected transmitter presets and FFE, CTLE, and DFE combinations through statistical and time-domain analysis, improved simulated eye opening on weak PCIe channels.
• Separated ISI and jitter contributions using channel simulations and waveform analysis, directed corrective work toward either interconnect geometry or transmitter/receiver equalization.
• Traced 0.8 dB of excess loss at 16 GHz to a via stub and evaluated backdrill and antipad alternatives in HFSS, recovered 0.6 dB in channel simulation.
• Qualified extracted interconnect models through mesh-convergence, material-sensitivity, port-order, and reference-impedance checks, prevented unstable or inconsistent networks from entering channel analysis.
• Resolved two low-margin DDR5 routing cases in HSPICE by comparing topology, ODT, driver-strength, skew, and length constraints, provided revised routing guidance for the board team.
• Selected controlled-impedance stackup geometries with layout and fabrication teams by balancing trace width, dielectric thickness, pair spacing, material loss, and manufacturing limitations.
• Identified reference-plane breaks and return-path discontinuities at layer transitions, specified ground stitching and return-via changes to reduce reflections, mode conversion, and coupling.
• Calibrated and de-embedded VNA/TDR coupon measurements and refined material and geometry models, achieved insertion-loss agreement within 0.7 dB at 16 GHz.
• Localized connector, breakout, and via impedance discontinuities using TDR overlays, gave layout engineers specific transition geometries for correction.
• Screened more than 100 Touchstone files for port mapping, passivity, mixed-mode conversion, and loss/crosstalk using Python, reduced board-revision triage from one day to two hours.
• Carried SI corrections through two prototype spins and confirmed revised geometries through post-layout extraction, updated model packages, and margin summaries.