DDR5-6400 · PCIe 5.0 · PDN · San Jose, CA

Signal and Power Integrity Engineer

Signal and power integrity engineer with 3+ years on high-speed memory and SerDes interfaces, across board- and package-level designs.

Email meLinkedInRésuméDownload PDF
SI/PI on high-speed memory and SerDes
3+ yrsSI/PI on high-speed memory and SerDes
Memory channel analysis
DDR5-6400Memory channel analysis
PCIe 5.0 channel evaluation
32 GT/sPCIe 5.0 channel evaluation
Insertion-loss correlation at 6 GHz
0.5 dBInsertion-loss correlation at 6 GHz

01Projects

02Experience

Rambus

Aug 2025 – Present

Signal Integrity and Power Integrity Engineer

  • DDR5-6400 channel analysis across 24 read/write and PVT cases
  • Insertion-loss correlation within 0.5 dB at 6 GHz
  • Weekly report preparation cut from 6 hours to 2 hours
Show all 12 contributionsHide contributions
  • Defined DDR5-6400 channel-analysis requirements for 24 read/write and PVT cases using HSPICE, Cadence Sigrity, buffer corners, and JESD79-5 timing criteria, identified the weakest evaluation-board byte lanes and converted the findings into routing and termination constraints.
  • Modeled package-to-PCB signal paths, BGA breakouts, and via transitions in HFSS 3D Layout, isolated dominant loss and reflection sources and provided geometry changes for post-layout review.
  • Optimized ODT, driver strength, and DQ-to-DQS skew across supported buffer corners, selecting settings and length constraints that improved margin on the weakest DDR5 byte lanes.
  • Analyzed NEXT/FEXT coupling, layer assignments, trace spacing, and reference-plane continuity, and recommended routing and ground-stitching changes to protect memory-channel eye opening.
  • Converted rail-noise allocations into regulator-to-package VDD/VDDQ PDN targets by modeling regulator, package, PCB, and decoupling behavior, and provided power-delivery guidance for board design reviews.
  • Investigated PDN antiresonance, ESR/ESL, and mounting-inductance effects in SIwave and OptimizePI, and selected capacitor values and placement changes that improved the modeled impedance profile.
  • Performed DC IR-drop and current-density analysis across copper paths and power/ground vias, specified wider delivery paths and revised via connections that were adopted in the next board spin.
  • Ranked decoupling alternatives using HSPICE load-step analysis for droop, overshoot, and settling behavior, selected the configuration with the strongest transient margin against the rail budget.
  • Established VNA, TDR, and oscilloscope test setups for channel loss, impedance, eye margin, and rail-noise measurements, created repeatable comparisons between board revisions.
  • Updated fixture, via, and channel models using measured data and achieved insertion-loss correlation within 0.5 dB at 6 GHz, improved confidence in simulation-based design decisions.
  • Automated Touchstone validation, corner sweeps, eye analysis, and impedance reporting with Python, reduced weekly report preparation time from 6 hours to 2 hours.
  • Coordinated three routing and decoupling changes with PCB layout and package-modeling teams, delivered channel and rail-margin evidence for design reviews and validation reruns.

AMD

Jun 2022 – Jul 2024

Signal Integrity Engineer

  • 32 GT/s PCIe 5.0 channels evaluated in Keysight ADS
  • Recovered 0.6 dB of a 0.8 dB via-stub loss at 16 GHz
  • Board-revision triage cut from one day to two hours
Show all 13 contributionsHide contributions
  • Evaluated 32 GT/s PCIe 5.0 channels in Keysight ADS by cascading package, PCB, connector, and via networks with IBIS-AMI models, ranked limiting channels for layout and equalization optimization.
  • Decomposed channel loss across packages, traces, connectors, and vias, identified the interconnect segments consuming the most eye and BER margin and prioritized them for corrective action.
  • Selected transmitter presets and FFE, CTLE, and DFE combinations through statistical and time-domain analysis, improved simulated eye opening on weak PCIe channels.
  • Separated ISI and jitter contributions using channel simulations and waveform analysis, directed corrective work toward either interconnect geometry or transmitter/receiver equalization.
  • Traced 0.8 dB of excess loss at 16 GHz to a via stub and evaluated backdrill and antipad alternatives in HFSS, recovered 0.6 dB in channel simulation.
  • Qualified extracted interconnect models through mesh-convergence, material-sensitivity, port-order, and reference-impedance checks, prevented unstable or inconsistent networks from entering channel analysis.
  • Resolved two low-margin DDR5 routing cases in HSPICE by comparing topology, ODT, driver-strength, skew, and length constraints, provided revised routing guidance for the board team.
  • Selected controlled-impedance stackup geometries with layout and fabrication teams by balancing trace width, dielectric thickness, pair spacing, material loss, and manufacturing limitations.
  • Identified reference-plane breaks and return-path discontinuities at layer transitions, specified ground stitching and return-via changes to reduce reflections, mode conversion, and coupling.
  • Calibrated and de-embedded VNA/TDR coupon measurements and refined material and geometry models, achieved insertion-loss agreement within 0.7 dB at 16 GHz.
  • Localized connector, breakout, and via impedance discontinuities using TDR overlays, gave layout engineers specific transition geometries for correction.
  • Screened more than 100 Touchstone files for port mapping, passivity, mixed-mode conversion, and loss/crosstalk using Python, reduced board-revision triage from one day to two hours.
  • Carried SI corrections through two prototype spins and confirmed revised geometries through post-layout extraction, updated model packages, and margin summaries.

03Skills

High-Speed Interfaces

  • DDR5
  • PCIe 5.0
  • SerDes
  • source-synchronous interfaces
  • HBM and 2.5D interposer studies

Signal Integrity

  • Transmission-line theory
  • controlled impedance
  • reflections
  • insertion loss
  • return loss
  • ISI
  • NEXT/FEXT crosstalk
  • differential signaling
  • skew
  • mode conversion
  • eye diagrams
  • jitter
  • BER
  • ODT
  • drive strength
  • FFE
  • CTLE
  • DFE

Power Integrity

  • PDN target impedance
  • AC impedance
  • DC IR drop
  • current density
  • load-step droop and overshoot
  • resonance and antiresonance
  • decoupling optimization
  • ESR/ESL
  • mounting inductance
  • regulator-package-board interaction
  • simultaneous switching noise

Modeling and Simulation

  • Ansys HFSS
  • HFSS 3D Layout
  • SIwave
  • Cadence Sigrity PowerSI
  • Cadence OptimizePI
  • Keysight ADS
  • Synopsys HSPICE
  • IBIS
  • IBIS-AMI
  • SPICE
  • Touchstone
  • S-parameters
  • RLGC models

PCB and Package Analysis

  • Stackup review
  • microstrip and stripline
  • BGA escape routing
  • vias and antipads
  • backdrilling
  • differential-pair spacing
  • reference planes
  • return paths
  • ground stitching
  • power and ground via allocation
  • fabrication tolerances

Laboratory Validation

  • Vector network analyzer
  • TDR
  • real-time oscilloscope
  • impedance measurement
  • S-parameter measurement
  • calibration
  • reference-plane setup
  • fixture de-embedding
  • probe-loading assessment
  • eye measurement
  • rail-noise measurement

Programming and Automation

  • Python
  • NumPy
  • SciPy
  • pandas
  • scikit-rf
  • Matplotlib
  • parameter sweeps
  • Touchstone parsing
  • model screening
  • CSV/HTML reporting
  • Git

Methodologies and Standards

  • Pre-layout analysis
  • post-layout verification
  • PVT and tolerance analysis
  • loss budgets
  • timing budgets
  • margin analysis
  • root-cause analysis
  • design reviews
  • JEDEC JESD79-5
  • PCI-SIG PCI Express Base Specification 5.0

04Education and certifications

Education

  • M.S., Management of Technology

    Arizona State University, Tempe, AZ

    Aug 2024 – May 2026

  • B.Tech, Electrical & Electronics Engineering

    Malla Reddy Engineering College (JNTU Hyderabad)

    2020 – 2023

Certifications

  • Transmission Lines 101, Dr. Eric Bogatin, The EEcosystem Electronics Masterclass
  • Essential Principles of Signal Integrity (EPSI), Dr. Eric Bogatin, Teledyne LeCroy
  • How to Read S-Parameters Like a Book, Dr. Eric Bogatin, The EEcosystem Electronics Masterclass

05Get in touch

Works with package, PCB layout, design, and validation teams to turn SI/PI failures into routing, termination, stackup, via, and power-delivery changes.

chetanjonnalagadda9@gmail.comLinkedIn